Copper pad structure

ABSTRACT

A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to semiconductorintegrated circuits and more particularly to the pads and solder ballsused to make electrical connections between the integrated circuitdevices having copper wiring and the external electrical environment.

[0003] 2. Description of the Related Art

[0004] Once the manufacturing processes for the last wiring layer of anintegrated circuit die is completed, additional processing is requiredto form connections between the die and its associated printed circuitcard or board. This additional processing allows connection to theexternal electrical environment and is sometimes referred to as “backend of line” or BEOL processing.

[0005] One aspect of BEOL processing can involve the formation oflead/tin solder balls, e.g. C4 connections, on the exterior of theintegrated circuit die. The solder balls are used to make electricalconnection to the last layer of wiring and underlying circuitrycontained on the integrated circuit device. In a later assembly process,the free surface of the solder ball is joined to corresponding wiringpads on a printed circuit card, flex circuit cable or ceramic diecarrier. FIG. 1 illustrates a cross section of a conventionallyfabricated integrated circuit device having aluminum wiring and solderball connections. More specifically, the exterior of the integratedcircuit has a passivation layer 12, typically comprised of silicondioxide, silicon nitride or silicon oxide/nitride combinations. Thepassivation layer 12 covers the aluminum last wiring layer 11 and thepassivation layer 12 contains an opening (via hole) that exposes thesurface of the last wiring layer. The passivation layer is not planar,but rather conformal to the underlying surface that contains the finalwiring layer. The via hole is conventionally formed using a standardlithographic and etching process.

[0006] Typically, a pad 13 (e.g., liner/barrier) is formed over the viahole. The pad 13 forms a “transition metallurgy” that provides a robustmechanical connection between the solder ball 14 and both the wiringlayer 11 and the passivation layer 12. The pad 13 also provides low andstable electrical (contact) resistance between the solder ball 14 andthe last wiring layer 11. The pad 13 is typically comprised, forexample, of one or more of chromium, tungsten or titanium withoverlayers of solderable metals such as copper or gold. Conventionally,the chromium, tungsten, etc. of the pad 13 are placed in contact withthe aluminum wiring layer 11 and the solderable metal(s) of the pad 13is placed in contact with the solder 14. During solder ball 14 formationon the integrated circuit and subsequent attachment of the solder balls14 to a printed circuit card, the lead or tin in the solder 14 maycompletely react with the solderable metal and bring lead or tin intocontact with the chromium, tungsten, etc. layer.

[0007] In the case of aluminum last wiring layers, there is limitedinter-metallic formation between the aluminum 11 and lead and tin in thesolder ball 14. Any tin that diffuses through micro cracks or grainboundaries of the pad 13 does not result in rapid, strong inter-metallicformation with aluminum. Also, with aluminum wiring, there isinsufficient reaction to consume the pad 13, i.e. react it intointer-metallic, or propagate inter-metallic into the aluminum wiringline.

[0008] However, high performance integrated circuits have introducedcopper as the last wiring layer. Copper has lower electrical resistancethan aluminum and, as a result, yields faster propagation of a signalthrough a wiring line, increasing the operational speed of theintegrated circuit. Copper however, readily reacts with (formsinter-metallics with) the tin 14. The copper-tin inter-metallics have anassociated volume change, that can be both mechanically weak and haveincreased electrical resistance. A mechanically weak inter-metallic candegrade the reliability, e.g. ability to withstand thermal cycles, ofthe integrated circuit device. The increased electrical resistance ofthe inter-metallic can also slow the signal propagation both between thedevice and its external connection and more particularly throughinternal device wiring.

[0009] When sufficient excess of tin exists in the solder ball 14, as inthe case of a solder ball made from eutectic solder (63% tin, 37% lead),inter-metallic formation can be extensive, extending well into thewiring lines degrading signal propagation and potentially damagingdielectric films adjacent to the wires, because of the volume changeassociated with inter-metallic formation. There is, therefore, a needfor an easy to manufacture pad structure which provides mechanically andelectrically robust interconnections between copper wiring and solderballs without introducing the possibility of tin or lead diffusion intothe last copper wiring lines. The invention described below providessuch a pad structure, in a planar configuration.

SUMMARY OF THE INVENTION

[0010] It is, therefore, an object of the present invention to provide astructure and method for forming mechanically and electrically robustinterconnections between integrated circuit copper wiring and solderballs, without possibility of tin or lead diffusion from the solderballs into the last copper wiring lines.

[0011] One embodiment of the invention comprises a metallurgicalstructure that includes a passivation layer, a via through thepassivation layer extending to a metal line within the metallurgicalstructure, a barrier layer lining the via, a metal plug in the via abovethe barrier layer, the metal plug and the metal line comprising a samematerial, and a solder bump formed on the metal plug.

[0012] The “same material” can be copper and the barrier layer can beone or more layers of Ti, TiN, Ta, and TaN. The barrier layer and themetal plug prevent elements within the solder bump from diff-using tothe metal line. The metal plug, the barrier layer and the passivationlayer form a planar exterior surface of the metallurgical structure. Thesolder ball can be in direct contact with the metal plug or thestructure can include a second barrier layer above the metal plug and asecond metal plug above the second barrier layer, where the second metalplug is in direct contact with the solder ball.

[0013] Another embodiment of the invention comprises a method of formingan integrated circuit structure that includes forming a via through anexterior of the integrated circuit structure to internal components ofthe integrated circuit structure, lining the via with a barrier layer,forming a plug above the barrier layer, the plug and the internalcomponents comprising a same material, and forming a connector on theplug.

[0014] The “same material” can again comprises copper, and the barrierlayer can comprise one or more layers of Ti, TiN, Ta, and TaN. Again,the barrier layer prevents elements within the connector from diffusingto the internal components.

[0015] The method also includes a process of polishing the integratedcircuit structure such that the plug, the barrier layer and the exteriorform a planar surface. The connector can be formed to be in directcontact with the plug or the inventive process can include forming asecond barrier layer above the plug and forming a second plug above thesecond barrier layer, such that the second plug is in direct contactwith the connector.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

[0017]FIG. 1 is a schematic diagram of a conventional via, pad, andsolder ball;

[0018]FIG. 2 is a schematic diagram of the inventive via, plug andsolder ball; and

[0019]FIG. 3 is a schematic diagram of another embodiment of theinventive via, plug and solder ball.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0020] As discussed above, conventional BEOL structures, such as thatshown in FIG. 1, suffer from the disadvantage that, when copper is usedas the last metalization layer, tin diffusion can result in a structurethat is not mechanically and electrically robust. The inventionovercomes these problems by using a novel copper plug and barrier layer,as discussed below.

[0021] A first embodiment of the invention is shown in FIG. 2. Theinvention replaces the conventional pad structure 13 as described abovewith the one shown in FIG. 2. The last copper wiring layer 20 on theintegrated circuit device is typically formed using a damascene processand is covered with an appropriate passivation films stack 21. Thepassivation films stack is typically comprised of one or more layers ofsilicon dioxide, silicon nitride or combinations thereof, deposited bychemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), etc. methods. An opening (via hole) 22 is formed inthe passivation films stack using conventional lithographic and etchingtechniques employing photoresist and reactive ion etching.

[0022] After removal of the photoresist, the stack of films 21 issequentially blanket deposited with a liner 23 and then a copper plug24. Initially, the “liner/barrier” film(s) 23 comprised of Ti, TiN, Ta,TaN, or combinations thereof is deposited by sputtering or reactivesputtering techniques. The total thickness of the liner films stack 23is between 100 and 1000 A thick. The liner films 23 are not limited tothose specified above, but as would be known by one ordinarily skilledin the art could be any substance that is selected to have theproperties of good adhesion to both copper wiring and the overlayerpassivation films, relatively low electrical resistance and excellentresistance to diffusion by lead, tin and copper.

[0023] Next, the copper plug 24 is deposited over the liner bysputtering, electroplating or evaporation techniques with sufficientthickness to be at least coplanar with the top of the passivation films21. Chemical mechanical polishing (CMP) is then used to remove thecopper 24 and the liner 23 from the field areas leaving a plug of liner23 and copper 24 in the via hole. If the passivation films stack 21 wasnot initially planar, the CMP process can be continued (with the same ora different slurry) after the liner is removed to planarize both thepassivation 21 and filled vias 22.

[0024] A lead/tin solder ball 25 is then formed on the via plug 24 usingevaporation through a mask, solder ink jet or other well knowntechniques. The amount of inter-metallic formation is controlled by theamount of tin in the solder ball and the thickness of the copper 24 inthe filled via 22 which in turn is controlled by the thickness of thepassivation films 21 and the liner 23.

[0025] A second embodiment of the invention, shown in FIG. 3, provides aredundant “liner/barrier” layer 35 in the filled via 22 to achieveminimum inter-metallic formation and maximum protection of theintegrated circuit copper wiring 20 from diffusion of elements containedin the solder ball. In this embodiment, the via 22 is filled asdescribed in the first embodiment. The copper 24 in the filled via 22 isthen selectively recessed using an aqueous solution of ammoniumpersulfate or other solution that will preferentially etch copper ratherthan the liner. Typically, the copper 24 is recessed between 1000 and10000 A to form a recessed copper plug 34 (e.g., copper plug 1). Asecond liner/barrier 35 comprised of Ti, TiN, Ta, TaN, or combinationsthereof are blanket deposited over the recessed copper plug 34 bysputtering or reactive sputtering techniques. A second copper film 36(e.g., copper plug 2) is deposited over the blanket liner/barrierfilm(s) by sputtering, electroplating or evaporation techniques withsufficient thickness to be at least coplanar with the top of thepassivation films.

[0026] Again the liner/barrier 35 thickness is controlled to be lessthan the amount which would be coplanar with the top of the passivationfilms stack, insuring that a thin copper film 36 remains in the centerof the via when the subsequent chemical, mechanical polish is complete.A lead/tin solder ball 37 is formed on the second via plug 36 usingevaporation through a mask, solder ink jet or other well-knowntechniques.

[0027] Therefore, the invention replaces the conventional liner 13 witha copper plug 24, 34, 36 and barrier 23, 35. This structure produces anumber of a advantages when compared to the conventional structure. Forexample, the copper plug/liner of the invention prevents tin diffusionto the underlying copper wiring layer 20. The copper plug consumes anytin which would otherwise diffuse to the underlying copper wiring. Theinvention is not limited to copper wiring. Instead, the invention isapplicable to any material with similar characteristics so long as theplug and the underlying wiring are of the same material. This allows theplug to consume the potential impurities before they reach theunderlying wiring layer. The barrier layer acts to stop any tinimpurities which are not consumed by the copper. Further, the inventionis different than structures which utilize a thin copper layer in thatthe copper plug provides sufficient thickness to consume large amountsof tin impurities and to form a strong inter-metallic bond with thelead/tin solder ball.

[0028] Additionally, the invention produces a structure which isco-planer with the passivation layer 21, which makes the formation ofthe lead/tin solder ball 25, 37 simpler and less prone to manufacturingdefect. Also, the physical strength of the copper plug/liner structureis superior to the conventional liner 13 (because copper makes a verystrong bond with tin/lead solder balls) and, therefore, providessuperior mechanical bonding strength between the integrated circuit andthe solder ball 25, 37.

[0029] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

What is claimed is:
 1. A metallurgical structure comprising: apassivation layer; a via through said passivation layer extending to ametal line within said metallurgical structure; a barrier layer liningsaid via; a metal plug in said via above said barrier layer, said metalplug and said metal line comprising a same material; and a solder bumpformed on said metal plug.
 2. The metallurgical structure in claim 1 ,wherein said same material comprises copper.
 3. The metallurgicalstructure in claim 1 , wherein said barrier layer comprises one or morelayers of Ti, TiN, Ta, and TaN.
 4. The metallurgical structure in claim1 , wherein said barrier layer and said metal plug prevent elementswithin said solder bump from diffusing to said metal line.
 5. Themetallurgical structure in claim 1 , wherein said metal plug, saidbarrier layer and said passivation layer form a planar exterior surfaceof said metallurgical structure.
 6. The metallurgical structure in claim1 , wherein said solder ball is in direct contact with said metal plug.7. The metallurgical structure in claim 1 , further comprising a secondbarrier layer above said metal plug and a second metal plug above saidsecond barrier layer, said second metal plug being in direct contactwith said solder ball.
 8. An integrated circuit structure comprising:internal components within an exterior covering; a via extending throughsaid exterior covering to said internal components; a barrier layerlining said via; a plug in said via above said barrier layer, said plugand said internal components comprising a same material; and a connectorformed on said plug.
 9. The integrated circuit structure in claim 8 ,wherein said same material comprises copper.
 10. The integrated circuitstructure in claim 8 , wherein said barrier layer comprises one or morelayers of Ti, TiN, Ta, and TaN.
 11. The integrated circuit structure inclaim 8 , wherein said barrier layer and said plug prevent elementswithin said connector from diffusing to said components.
 12. Theintegrated circuit structure in claim 8 , said plug, said barrier layerand said exterior covering form a planar exterior surface of saidintegrated circuit structure.
 13. The integrated circuit structure inclaim 8 , wherein said connector is in direct contact with said plug.14. The integrated circuit structure in claim 8 , further comprising asecond barrier layer above said plug and a second plug above said secondbarrier layer, said second plug being in direct contact with saidconnector.
 15. A method of forming an integrated circuit structurecomprising: forming a via through an exterior of said integrated circuitstructure to internal components of said integrated circuit structure;lining said via with a barrier layer; forming a plug above said barrierlayer, said plug and said internal components comprising a samematerial; and forming a connector on said plug.
 16. The method in claim15 , wherein said same material comprises copper.
 17. The method inclaim 15 , wherein said barrier layer comprises one or more layers ofTi, TiN, Ta, and TaN.
 18. The method in claim 15 , wherein said barrierlayer prevents elements within said connector from diffusing to saidinternal components.
 19. The method in claim 15 , further comprisingpolishing said integrated circuit structure such that said plug, saidbarrier layer and said exterior form a planar surface.
 20. The method inclaim 15 , wherein said connector is formed to be in direct contact withsaid plug.
 21. The method in claim 15 , further comprising forming asecond barrier layer above said plug and forming a second plug abovesaid second barrier layer, such that said second plug is in directcontact with said connector.